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1/32 february 2005 stm690, stm704, stm795 stm802, stm804, stm805, stm806 3v supervisor with battery switchover * contact local st sales office for availability. features summary rst or rst outputs nvram supervisor for external lpsram chip-enable gating (stm795 only) for external lpsram (7ns max prop delay) manual (push-button) reset input 200ms (typ) t rec watchdog timer - 1.6sec (typ) automatic battery switchover low battery supply current - 0.4a (typ) power-fail comparator (pfi/pfo ) low supply current - 40a (typ) guaranteed rst (rst) assertion down to v cc = 1.0v operating temperature: ?40c to 85c (industrial grade) figure 1. packages table 1. device options note: 1. all rst outputs push-pull (unless otherwise noted) 2. open drain output. 8 1 so8 (m) tssop8 3x3 (ds)* watchdog input active- low rst (1) active- high rst manual reset input battery switch-over power-fail compar- ator chip- enable gating stm690t/s/r ?? ?? stm704t/s/r ???? stm795t/s/r ? (2) ?? stm802t/s/r ?? ?? stm804t/s/r ? ? (2) ?? stm805t/s/r ? ? (2) ?? stm806t/s/r ????
stm690/704/ 795/802/804/805/806 2/32 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 1. device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram (stm690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. logic diagram (stm704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. logic diagram (stm795). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 5. stm690/802/804/805 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 6. stm704/806 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 7. stm795 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 8. block diagram (stm690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 9. block diagram (stm704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 10.block diagram (stm795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 11.hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 push-button reset input (stm704/806). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 watchdog input (not available on stm704/795/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 back-up battery switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. i/o status in battery back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 chip-enable gating (stm795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 chip enable input (stm795 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 chip enable output (stm795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 figure 12.chip-enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 13.chip enable waveform (stm795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 power-fail input/output (not available on stm795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 14.power-fail comparator waveform (stm690/704/802/804/805/806) . . . . . . . . . . . . . . . . 11 using a supercap? as a backup power source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 15.using a supercap? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 negative-going v cc transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 16.v cc -to-v out on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 17.v bat -to-v out on-resistance vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 18.supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 19.battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figure 20.v pfi threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/32 stm690/704/ 795/802/804/805/806 figure 21.reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 22.power-up t rec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 23.normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 24.watchdog time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 25.e to e con on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 26.pfi to pfo propagation delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 27.output voltage vs. load current (v cc = 5v; v bat = 2.8v; t a = 25c). . . . . . . . . . . . . . 18 figure 28.output voltage vs. load current (v cc = 0v; v bat = 2.8v; t a = 25c). . . . . . . . . . . . . . 19 figure 29.rst output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 30.rst output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 31.power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 32.power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 33.maximum transient duration vs. reset threshold overdrive. . . . . . . . . . . . . . . . . . . . . 21 figure 34.e to e con propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 35.e to e con propagation delay test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 36.ac testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 37.mr timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 38.watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 39.so8 ? 8-lead plastic small outline, 150 mils body width, package mech. drawing. . . . 27 table 8. so8 ? 8-lead plastic small outline, 150 mils body width, package mechanical data . . 27 figure 40.tssop8 ? 8-lead, thin shrink small outline, 3x3mm body size, outline . . . . . . . . . . . 28 table 9. tssop8 ? 8-lead, thin shrink small outline, 3x3mm body size, mechanical data . . . . 28 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 10. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 table 11. marking description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
stm690/704/ 795/802/804/805/806 4/32 summary description the stm690/704/795/802/804/805/806 supervi- sors are self-contained devices which provide mi- croprocessor supervisory functions with the ability to non-volatize and write-protect external lpsram. a precision voltage reference and com- parator monitors the v cc input for an out-of-toler- ance condition. when an invalid v cc condition occurs, the reset output (rst ) is forced low (or high in the case of rst). these devices also offer a watchdog timer (except for stm704/795/806) as well as a power-fail comparator (except for stm795) to provide the system with an early warning of impending power failure. these devices are available in a standard 8-pin soic package or a space-saving 8-pin tssop package. figure 2. logic diagram (stm690/802/804/805) note: 1. for stm804/805, reset output is active-high and open drain. figure 3. logic diagram (stm704/806) figure 4. logic diagram (stm795) table 2. signal names note: 1. open drain for stm804/805 only. 2. stm795 ai08846 v cc v bat stm690/ 802/804/ 805 v ss v out rst(rst) (1) wdi pfi pfo ai08847 v cc v bat stm704 stm806 v ss v out rst mr pfi pfo mr push-button reset input wdi watchdog input rst active-low reset output rst (1) active-high reset output e (2) chip enable input e con (2) conditioned chip enable output vccsw (2) v cc switch output v out supply voltage output v cc supply voltage v bat back-up supply voltage pfi power-fail input pfo power-fail output v ss ground ai08848 v cc v bat stm795 v ss v out rst v ccsw e e con
5/32 stm690/704/ 795/802/804/805/806 figure 5. stm690/802/804/805 connections note: 1. for stm804/805, reset output is active-high and open drain. figure 6. stm704/806 connections figure 7. stm795 connections 1 pfo pfi wdi rst(rst) (1) v cc v out v bat v ss ai08849 so8/tssop8 2 3 4 8 7 6 5 1 pfo pfi mr rst v cc v out v bat v ss ai08850 so8/tssop8 2 3 4 8 7 6 5 1 e con v ss rst v cc v out v bat v ccsw ai08851 so8/tssop8 2 3 4 8 7 6 5 e
stm690/704/ 795/802/804/805/806 6/32 pin descriptions mr . a logic low on /mr asserts the reset output. reset remains asserted as long as mr is low and for t rec after mr returns high. this active-low input has an internal pull-up. it can be driven from a ttl or cmos logic line, or shorted to ground with a switch. leave open if unused. wdi. if wdi remains high or low for 1.6sec, the in- ternal watchdog timer runs out and reset is trig- gered. the internal watchdog timer clears while reset is asserted or when wdi sees a rising or fall- ing edge. the watchdog function cannot be disabled by al- lowing the wdi pin to float. rst . pulses low for t rec when triggered, and stays low whenever v cc is below the reset threshold or when mr is a logic low. it remains low for t rec after either v cc rises above the reset threshold, the watchdog triggers a reset, or mr goes from low to high. rst (open drain). pulses high for t rec when trig- gered, and stays high whenever v cc is above the reset threshold or when mr is a logic high. it re- mains high for t rec after either v cc falls below the reset threshold, the watchdog triggers a reset, or mr goes from high to low. pfi. when pfi is less than v pfi or when v cc falls below v sw (2.4v), pfo goes low; otherwise, pfo remains high. connect to ground if unused. pfo . when pfi is less than v pfi , or v cc falls be- low v sw , pfo goes low; otherwise, pfo remains high. leave open if unused. v out . when v cc is above the switchover voltage (v so ), v out is connected to v cc through a p- channel mosfet switch. when v cc falls below v so , v bat connects to v out . connect to v cc if no battery is used. vccsw . when v out switches to battery, vccsw is high. when v out switches back to v cc , vccsw is low. it can be used to drive gate of external pmos transistor for i out requirements exceeding 75ma. e . the input to the chip-enable gating circuit. con- nect to ground if unused. e con . e con goes low only when e is low and re- set is not asserted. if e con is low when reset is as- serted, e con will remain low for 15s or until e goes high, whichever occurs first. in the disabled mode, e con is pulled up to v out . v bat . when v cc falls below v so , v out switches from v cc to v bat . when v cc rises above v so + hysteresis, v out reconnects to v cc . v bat may ex- ceed v cc . connect to v cc if no battery is used. table 3. pin description pin name function stm795 stm690 stm802 stm704 stm806 stm804 stm805 ??6?mr push-button reset input ?6?6wdiwatchdog input 777?rst active-low reset output ???7rstactive-high reset output ?444pfipfi power-fail i nput ?555pfo pfo power-fail output 1111 v out supply output for external lpsram 2222 v cc supply voltage 3???vccsw v cc switch output 4333 v ss ground 5???e chip enable input 6??? e con conditioned chip enable output 8888 v bat backup-battery input
7/32 stm690/704/ 795/802/804/805/806 figure 8. block diagram (stm690/802/804/805) note: 1. for stm804/805, reset output is active-high and open drain. figure 9. block diagram (stm704/806) ai07897 watchdog timer v rst v out compare compare compare t rec generator v pfi v bat v so v cc pfi wdi rst(rst) (1) pfo ai07898 v rst v out compare compare compare t rec generator v pfi v bat v so v cc pfi mr rst pfo
stm690/704/ 795/802/804/805/806 8/32 figure 10. block diagram (stm795) figure 11. hardware hookup note: 1. for stm690/802/804/805. 2. for stm795 only. 3. not available on stm795. 4. for stm704/806. ai08852 v rst v out v ccsw e con compare compare compare t rec generator e con output control v pfi v bat v so v cc pfi rst pfo e e v cc ai08853 v cc e con (2) mr (4) v out v ccsw (2) e v cc lpsram pfi (3) 0.1 f 0.1 f stm690/704/ 795/802/804/ 805/806 wdi (1) pfo (3) rst to microprocessor reset unregulated voltage regulator v cc v in r1 r2 push-button from microprocessor e (2) v bat to microprocessor nmi
9/32 stm690/704/ 795/802/804/805/806 operation reset output the stm690/704/795/802/804/805/806 supervi- sor asserts a reset signal to the mcu whenever v cc goes below the reset threshold (v rst ), a watchdog time-out occurs, or when the push-but- ton reset input (mr ) is taken low. rst is guaran- teed to be a logic low (logic high for stm804/805) for 0v < v cc < v rst if v bat is greater than 1v. without a back-up battery, rst is guaranteed val- id down to v cc =1v. during power-up, once v cc exceeds the reset threshold an internal timer keeps rst low for the reset time-out period, t rec . after this interval rst returns high. if v cc drops below the reset threshold, rst goes low. each time rst is asserted, it stays low for at least the reset time-out period (t rec ). any time v cc goes below the reset threshold the internal timer clears. the reset timer starts when v cc returns above the reset threshold. push-button reset input (stm704/806) a logic low on mr asserts reset. reset remains asserted while mr is low, and for t rec (see figure 37., page 24 ) after it returns high. the mr input has an internal 40k ? pull-up resistor, allowing it to be left open if not used. this input can be driven with ttl/cmos-logic levels or with open-drain/ collector outputs. connect a normally open mo- mentary switch from mr to gnd to create a man- ual reset function; external debounce circuitry is not required. if mr is driven from long cables or the device is used in a noisy environment, connect a 0.1f capacitor from mr to gnd to provide ad- ditional noise immunity. mr may float, or be tied to v cc when not used. watchdog input (not available on stm704/ 795/806) the watchdog timer can be used to detect an out- of-control mcu. if the mcu does not toggle the watchdog input (wdi) within t wd (1.6sec typ), the reset is asserted. the internal watchdog timer is cleared by either: 1. a reset pulse, or 2. by toggling wdi (high-to-low or low-to-high), which can detect pulses as short as 50ns. if wdi is tied high or low, a reset pulse is triggered every 1.8sec (t wd + t rec ). the timer remains cleared and does not count for as long as reset is asserted. as soon as reset is re- leased, the timer starts counting (see figure 38., page 24 ). note: input frequency greater than 20ns (50mhz) will be filtered. back-up battery switchover in the event of a power failure, it may be necessary to preserve the contents of external sram through v out . with a backup battery installed with voltage v bat , the devices automatically switch the sram to the back-up supply when v cc falls. note: if back-up battery is not used, connect both v bat and v out to v cc . this family of supervisors does not always con- nect v bat to v out when v bat is greater than v cc . v bat connects to v out (through a 100 ? switch) when v cc is below v sw (2.4v) or v bat (whichever is lower). this is done to allow the back-up battery (e.g., a 3.6v lithium cell) to have a higher voltage than v cc . assuming that v bat > 2.0v, switchover at v so en- sures that battery back-up mode is entered before v out gets too close to the 2.0v minimum required to reliably retain data in most external srams. when v cc recovers, hysteresis is used to avoid oscillation around the v so point. v out is connect- ed to v cc through a 3 ? pmos power switch. note: the back-up battery may be removed while v cc is valid, assuming v bat is adequately decou- pled (0.1f typ), without danger of triggering a re- set. table 4. i/o status in battery back-up pin status v out connected to v bat through internal switch v cc disconnected from v out pfi disabled pfo logic low e high impedance e con logic high wdi watchdog timer is disabled mr disabled rst logic low rst logic high v bat connected to v out vccsw logic high (stm795)
stm690/704/ 795/802/804/805/806 10/32 chip-enable gating (stm795 only) internal gating of the chip enable (e ) signal pre- vents erroneous data from corrupting the external cmos ram in the event of an undervoltage con- dition. the stm795 uses a series transmission gate from e to e con (see figure 12 ). during nor- mal operation (reset not asserted), the e transmis- sion gate is enabled and passes all e transitions. when reset is asserted, this path becomes dis- abled, preventing erroneous data from corrupting the cmos ram. the short e propagation delay from e to e con enables the stm795 to be used with most ps. if e is low when reset asserts, e con remains low for typically 10s to permit the current write cycle to complete. chip enable input (stm795 only) the chip-enable transmission gate is disabled and e is high impedance (disabled mode) while reset is asserted. during a power-down sequence when v cc passes the reset threshold, the chip-enable transmission gate disables and e immediately be- comes high impedance if the voltage at e is high. if e is low when reset asserts, the chip-enable transmission gate will disable 10s after reset as- serts (see figure 13 ). this permits the current write cycle to complete during power-down. any time a reset is generated, the chip-enable transmission gate remains disabled and e remains high impedance (regardless of e activity) for the first half of the reset time-out period (t rec /2). when the chip enable transmission gate is enabled, the impedance of e appears as a 40 ? resistor in se- ries with the load at e con . the propagation delay through the chip-enable transmission gate de- pends on v cc , the source impedance of the drive connected to e , and the loading on e con . the chip enable propagation delay is production tested from the 50% point on e to the 50% point on e con using a 50 ? driver and a 50pf load capacitance (see figure 36., page 23 ). for minimum propaga- tion delay, minimize the capacitive load at e con and use a low-output impedance driver. chip enable output (stm795 only) when the chip-enable transmission gate is en- abled, the impedance of e con is equivalent to a 40 ? resistor in series with the source driving e . in the disabled mode, the transmission gate is off and an active pull-up connects e con to v out (see figure 12 ). this pull-up turns off when the trans- mission gate is enabled. figure 12. chip-enable gating figure 13. chip enable waveform (stm795) ai08802 v rst v out v cc compare e con t rec generator e con output control rst e ai08855b rst e v cc v rst v bat e con trec trec ? trec ? trec 10s
11/32 stm690/704/ 795/802/804/805/806 power-fail input/output (not available on stm795) the power-fail input (pfi) is compared to an inter- nal reference voltage (independent from the v rst comparator). if pfi is less than the power-fail threshold (v pfi ), the power-fail output (pfo ) will go low. this function is intended for use as an un- dervoltage detector to signal a failing power sup- ply. typically pfi is connected through an external voltage divider (see figure 11., page 8 ) to either the unregulated dc input (if it is available) or the regulated output of the v cc regulator. the voltage divider can be set up such that the voltage at pfi falls below v pfi several milliseconds before the regulated v cc input to the stm690/704/795/802/ 804/805/806 or the microprocessor drops below the minimum operating voltage. during battery back-up, the power-fail comparator is turned off and pfo goes (or remains) low (see figure 14., page 11 ). this occurs after v cc drops below v sw (2.4v). when power returns, the pow- er-fail comparator is enabled and pfo follows pfi. if the comparator is unused, pfi should be con- nected to v ss and pfo left unconnected. pfo may be connected to mr on the stm704/806 so that a low voltage on pfi will generate a reset out- put. applications information these supervisor circuits are not short-circuit pro- tected. shorting v out to ground - excluding pow- er-up transients such as charging a decoupling capacitor - destroys the device. decouple both v cc and v bat pins to ground by placing 0.1f ca- pacitors as close to the device as possible. figure 14. power-fail comparator waveform (stm690/704/802/804/805/806) ai08861a v cc v rst v sw (2.4v) trec rst pfo pfo follows pfi pfo follows pfi
stm690/704/ 795/802/804/805/806 12/32 using a supercap? as a backup power source supercaps? are capacitors with extremely high capacitance values (e.g., order of 0.47f) for their size. figure 15 shows how to use a supercap as a back-up power source. the supercap may be connected through a diode to the v cc supply. since v bat can exceed v cc while v cc is above the reset threshold, there are no special precau- tions when using these supervisors with a super- cap. figure 15. using a supercap? negative-going v cc transients the stm690/704/795/802/804/805/806 supervi- sors are relatively immune to negative-going v cc transients (glitches). figure 33., page 21 was gen- erated using a negative pulse applied to v cc , starting at v rst + 0.3v and ending below the reset threshold by the magnitude indicated (comparator overdrive). the graph indicates the maximum pulse width a negative v cc transient can have without causing a reset pulse. as the magnitude of the transient increases (further below the thresh- old), the maximum allowable pulse width decreas- es. any combination of duration and overdrive which lies under the curve will not generate a re- set signal. typically, a v cc transient that goes 100mv below the reset threshold and lasts 40s or less will not cause a reset pulse. a 0.1f bypass capacitor mounted as close as possible to the v cc pin provides additional transient immunity. ai08805 stmxxx v bat v cc v out 5v gnd rst to external sram to p
13/32 stm690/704/ 795/802/804/805/806 typical operating characteristics note: typical values are at t a = 25c. figure 16. v cc -to-v out on-resistance vs. temperature figure 17. v bat -to-v out on-resistance vs. temperature 0.0 1.0 2.0 3.0 4.0 5.0 ?40 ?20 0 20 40 60 80 100 120 temperature ( c) v cc -to-v out on-resistance ( ? ) v cc = 3.0v v cc = 4.5v v cc = 5.5v ai10498 temperature ( c) v bat - to - v out on-resistance ( ? ) ai09140b 0 20 40 60 80 100 120 140 160 ?40 ?20 0 20 40 60 80 100 120 v bat = 2.0v v bat = 3.0v v bat = 3.3v v bat = 3.6v
stm690/704/ 795/802/804/805/806 14/32 figure 18. supply current vs. temperature (no load) figure 19. battery current vs. temperature temperature ( c) supply current (a) ai09141b 0 5 10 15 20 25 30 ?40 ?20 0 20 40 60 80 100 120 v cc = 2.7v v cc = 3.0v v cc = 3.6v v cc = 4.5v v cc = 5.5v temperature ( c) battery supply current (na) 0.1 1 10 100 1000 ?40 ?20 0 20 40 60 80 100 120 v bat = 2.0v v bat = 3.0v v bat = 3.6v ai10499
15/32 stm690/704/ 795/802/804/805/806 figure 20. v pfi threshold vs. temperature figure 21. reset comparator propagation delay vs. temperature temperature ( c) v pfi threshold (v) ai09142b 1.225 1.230 1.235 1.240 1.245 1.250 1.255 1.260 1.265 1.270 ?40 ?20 0 20 40 60 80 100 120 v cc = 2.5v v cc = 3.0v v cc = 3.3v v cc = 3.6v temperature ( c) propagation delay (s) ai09143b 10 12 14 16 18 20 22 24 26 28 30 ?40 ?20 0 20 40 60 80 100 120
stm690/704/ 795/802/804/805/806 16/32 figure 22. power-up t rec vs. temperature figure 23. normalized reset threshold vs. temperature ai09144b temperature ( c) t rec (ms) 210 215 220 225 230 235 240 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 4.5v v cc = 5.5v temperature ( c) normalized reset threshold ai09145b 0.996 0.998 1.000 1.002 1.004 ?40 ?20 0 20 40 60 80 100 120
17/32 stm690/704/ 795/802/804/805/806 figure 24. watchdog time-out period vs. temperature figure 25. e to e con on-resistance vs. temperature temperature ( c) watchdog time-out period (sec) ai09146b 1.60 1.65 1.70 1.75 1.80 1.85 1.90 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 4.5v v cc = 5.5v temperature ( c) e to e con on-resistance ( ? ) ai09147b 0 10 20 30 40 50 60 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 4.5v v cc = 5.5v
stm690/704/ 795/802/804/805/806 18/32 figure 26. pfi to pfo propagation delay vs. temperature figure 27. output voltage vs. load current (v cc = 5v; v bat = 2.8v; t a = 25c) temperature ( c) ai09148b pfi to pfo propagation delay (s) 0.0 1.0 2.0 3.0 4.0 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 3.6v v cc = 4.5v v cc = 5.5v 4.94 4.96 4.98 5.00 0 1020304050 i out (ma) v out (v) ai10496
19/32 stm690/704/ 795/802/804/805/806 figure 28. output voltage vs. load current (v cc = 0v; v bat = 2.8v; t a = 25c) figure 29. rst output voltage vs. supply voltage 2.66 2.68 2.70 2.72 2.74 2.76 2.78 2.80 0.0 0.2 0.4 0.6 0.8 1.0 i out (ma) v out (v) ai10497 v rst (v) v cc (v) ai09149b 0 1 2 3 4 5 0 1 2 3 v rst v cc 4 5 500ms/div
stm690/704/ 795/802/804/805/806 20/32 figure 30. rst output voltage vs. supply voltage figure 31. power-fail comparator response time (assertion) v rst (v) v cc (v) ai09150b 0 1 2 3 4 5 0 1 2 3 4 5 v rst v cc 500ms/div 5v 1.3v pfi 1v/div 0v 500mv/div 0v 500ns/div ai09153b pfo
21/32 stm690/704/ 795/802/804/805/806 figure 32. power-fail comparator response time (de-assertion) figure 33. maximum transient duration vs. reset threshold overdrive ai09154b 5v 1.3v pfi 1v/div 0v 500mv/div 0v 500ns/div pfo reset comparator overdrive, v rst ? v cc (v) reset occurs above the curve. transient duration (s) ai09156b 0 1000 2000 3000 4000 5000 6000 0.001 0.01 0.1 1 10
stm690/704/ 795/802/804/805/806 22/32 figure 34. e to e con propagation delay vs. temperature maximum rating stressing the device above the rating listed in the absolute maximum ratings? table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 5. absolute maximum ratings note: 1. reflow at peak temperature of 255c to 260c for < 30 seconds (total thermal budget not to exceed 180c for between 90 t o 150 seconds). temperature ( c) e to e con propagation delay (ns) ai09157b 0.0 1.0 2.0 3.0 4.0 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 4.5v v cc = 5.5v symbol parameter value unit t stg storage temperature (v cc off) ?55 to 150 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltage ?0.3 to v cc +0.3 v v cc /v bat supply voltage ?0.3 to 6.0 v i o output current 20 ma p d power dissipation 320 mw
23/32 stm690/704/ 795/802/804/805/806 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 6 , operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 6. operating and ac measurement conditions figure 35. e to e con propagation delay test circuit note: 1. c l includes load capacitance and scope probe capacitance. figure 36. ac testing input/output waveforms parameter stm690/704/795/ 802/804/805/806 unit v cc /v bat supply voltage 1.0 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c input rise and fall times 5ns input pulse voltages 0.2 to 0.8v cc v input and output timing ref. voltages 0.3 to 0.7v cc v ai08854 v bat e con v cc v cc 3.6v 50pf c l (1) 25 ? equivalent source impedance 50 ? cable 50 ? 50 ? stm690/704/ 795/802/804/ 805/806 gnd e ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc
stm690/704/ 795/802/804/805/806 24/32 figure 37. mr timing waveform note: 1. rst for stm805. figure 38. watchdog timing table 7. dc and ac characteristics sym alter- native description test condition (1) min typ max unit v cc , v bat (2) operating voltage t a = ?40 to +85c 1.1 (3) 5.5 v i cc v cc supply current excluding i out (v cc < 5.5v) 40 60 a excluding i out (v cc < 3.6v) 35 50 a v cc supply current in battery back-up mode excluding i out (v bat = 2.3v, v cc = 2.0v, mr = v cc ) 25 35 a i bat (4) v bat supply current in battery back-up mode excluding i out (v bat = 3.6v) 0.4 1.0 a v out1 v out voltage (active) i out1 = 5ma (5) v cc ? 0.03 v cc ? 0.015 v i out1 = 75ma v cc ? 0.3 v cc ? 0.15 v i out1 = 250a, v cc > 2.5v (5) v cc ? 0.0015 v cc ? 0.0006 v v out2 v out voltage (battery back-up) i out2 = 250a, v bat = 2.3v v bat ? 0.1 v bat ? 0.034 v i out2 = 1ma, v bat = 2.3v v bat ? 0.14 v v cc to v out on-resistance 34 ? v bat to v out on-resistance 100 ? ai07837a rst (1) mr tmlrl trec tmlmh ai07891 rst wdi v cc trec twd
25/32 stm690/704/ 795/802/804/805/806 i li input leakage current (mr ) stm704/806 only; mr = 0v, v cc = 3v 20 75 350 a input leakage current (pfi) 0v = v in = v cc ?25 2 +25 na input leakage current (wdi) 0v = v in = v cc ?1 +1 a i lo output leakage current stm804/805/795; 0v = v in = v cc (6) ?1 +1 a v ih input high voltage (mr , wdi) v rst (max) < v cc < 5.5v 0.7v cc v v il input low voltage (mr , wdi) v rst (max) < v cc < 5.5v 0.3v cc v v ol output low voltage (pfo , rst , rst, vccsw ) v cc = v rst (max), i sink = 3.2ma 0.3 v output low voltage (e con ) v cc = v rst (max), i out = 1.6ma, e = 0v 0.2v cc v v ol output low voltage (rst ) i ol = 40a, v cc = 1.0v, v bat = v cc , t a = 0c to 85c 0.3 v i ol = 200a, v cc = 1.2v, v bat = v cc 0.3 v v oh output high voltage (rst , rst) (7) i source = 1ma, v cc = v rst (max) 2.4 v output high voltage (e con ) v cc = v rst (max), i out = 1.6ma, e = v cc 0.8v cc v output high voltage (pfo ) i source = 75a, v cc = v rst (max) 0.8v cc v v ohb v oh battery back-up (v ccsw , rst) i source = 100a, v cc = 0v, v bat = 2.8v 0.8v bat v v oh battery back-up (e con ) i source = 75a, v cc = 0v, v bat = 2.8v 0.8v bat v power-fail comparator (not available on stm795) v pfi pfi input threshold pfi falling (v cc < 3.6v) stm802/ 804/806 1.212 1.237 1.262 v stm690/ 704/805 1.187 1.237 1.287 v pfi hysteresis pfi rising (v cc < 3.6v) 10 20 mv t pfd pfi to pfo propagation delay 2s i sc pfo output short to gnd current v cc = 3.6v, pfo = 0v 0.1 0.75 2.0 ma battery switchover v so battery back-up switchover voltage (8,9) power-down v bat > v sw v sw v v bat < v sw v bat v power-up v bat > v sw v sw v v bat < v sw v bat v v sw 2.4 v hysteresis 40 mv sym alter- native description test condition (1) min typ max unit
stm690/704/ 795/802/804/805/806 26/32 note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = v rst (max) to 5.5v; and v bat = 2.8v (except where noted). 2. v cc supply current, logic input leakage, watchdog functionality, push-button reset functionality, pfi functionality, state of rst and rst tested at v bat = 3.6v, and v cc = 5.5v. the state of rst or rst and pfo is tested at v cc = v cc (min). either v cc or v bat can go to 0v if the other is greater than 2.0v. 3. v cc (min) = 1.0v for t a = 0c to +85c. 4. tested at v bat = 3.6v, v cc = 3.5v and 0v. 5. guaranteed by design. 6. the leakage current measured on the rst pin (stm804/805) or rst pin (stm795) is tested with the reset output not asserted (output high impedance). 7. not valid for stm795/804/805 (open drain). 8. when v bat > v cc > v sw , v out remains connected to v cc until v cc drops below v sw . 9. when v sw > v cc > v bat , v out remains connected to v cc until v cc drops below the battery voltage (v bat ) ? 75mv. 10. the reset threshold tolerance is wider for v cc rising than for v cc falling due to the 10mv (typ) hysteresis, which prevents internal oscillation. reset thresholds v rst (10) reset threshold stm690t/ 704t/795t/ 805t v cc falling 3.00 3.075 3.15 v v cc rising 3.00 3.085 3.17 v stm802t/ 804t/806t v cc falling 3.00 3.075 3.12 v v cc rising 3.00 3.085 3.14 v stm690s/ 704s/795s/ 805s v cc falling 2.85 2.925 3.00 v v cc rising 2.85 2.935 3.02 v stm802s/ 804s/806s v cc falling 2.88 2.925 3.00 v v cc rising 2.88 2.935 3.02 v stm690r/ 704r/795r/ 805r v cc falling 2.55 2.625 2.70 v v cc rising 2.55 2.635 2.72 v stm802r/ 804r/806r v cc falling 2.59 2.625 2.70 v v cc rising 2.59 2.635 2.72 v t rec rst pulse width v cc < 3.6v 140 200 280 ms push-button reset input (stm704/806) t mlmh t mr mr pulse width 100 20 ns t mlrl t mrd mr to rst output delay 60 500 ns watchdog timer (not available on stm704/795/806) t wd watchdog timeout period v rst (max) < v cc < 3.6v 1.12 1.60 2.24 s wdi pulse width v rst (max) < v cc < 3.6v 100 20 ns chip-enable gating (stm795 only) e -to-e con resistance v cc = v rst (max) 46 ? e -to-e con propagation delay v cc = v rst (max) 27ns reset-to-e con high delay 10 s i sc e con short circuit current v cc = 3.6v, disable mode, e con = 0v 0.1 0.75 2.0 ma sym alter- native description test condition (1) min typ max unit
27/32 stm690/704/ 795/802/804/805/806 package mechanical figure 39. so8 ? 8-lead plastic small outline, 150 mils body width, package mech. drawing note: drawing is not to scale. table 8. so8 ? 8-lead plastic small outline, 150 mils body width, package mechanical data symb mm inches typ min max typ min max a ? 1.35 1.75 ? 0.053 0.069 a1 ? 0.10 0.25 ? 0.004 0.010 b ? 0.33 0.51 ? 0.013 0.020 c ? 0.19 0.25 ? 0.007 0.010 d ? 4.80 5.00 ? 0.189 0.197 ddd ? ?0.10? ?0.004 e ? 3.80 4.00 ? 0.150 0.157 e1.27? ?0.050? ? h ? 5.80 6.20 ? 0.228 0.244 h ? 0.25 0.50 ? 0.010 0.020 l ? 0.40 0.90 ? 0.016 0.035 ?08?08 n8 8 so-a e 8 ddd b e a d c l a1 1 h h x 45? a2
stm690/704/ 795/802/804/805/806 28/32 figure 40. tssop8 ? 8-lead, thin shrink small outline, 3x3mm body size, outline note: drawing is not to scale. table 9. tssop8 ? 8-lead, thin shrink small outline, 3x3mm body size, mechanical data symb mm inches typ min max typ min max a ? ?1.10? ?0.043 a1 ? 0.05 0.15 ? 0.002 0.006 a2 0.85 0.75 0.95 0.034 0.030 0.037 b ? 0.25 0.40 ? 0.010 0.016 c ? 0.13 0.23 ? 0.005 0.009 cp ? ? 0.10 ? ? 0.004 d 3.00 2.90 3.10 0.118 0.114 0.122 e0.65? ?0.026? ? e 4.90 4.65 5.15 0.193 0.183 0.203 e1 3.00 2.90 3.10 0.118 0.114 0.122 l 0.55 0.40 0.70 0.022 0.016 0.030 l1 0.95 ? ? 0.037 ? ? ?06?06 n8 8 tssop8bm 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
29/32 stm690/704/ 795/802/804/805/806 part numbering table 10. ordering information scheme note: 1. contact local st sales office for availability. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: stm690 t m 6 e device type stm690/704/795/802/804/805/806 reset threshold voltage t = stm690/704/795/805 = v rst = 3.00v to 3.15v stm802/804/806 = v rst = 3.00v to 3.12v s = stm690/704/795/805 = v rst = 2.85v to 3.00v stm802/804/806 = v rst = 2.88v to 3.00v r = stm690/704/795/805 = v rst = 2.55v to 2.70v stm802/804/806 = v rst = 2.59v to 2.70v package m = so8 ds (1) = tssop8 temperature range 6 = ?40 to 85c shipping method e = tubes f = tape & reel
stm690/704/ 795/802/804/805/806 30/32 table 11. marking description part number reset threshold package topside marking stm690t 3.075 so8 690t tssop8 stm690s 2.925 so8 690s tssop8 stm690r 2.625 so8 690r tssop8 stm704t 3.075 so8 704t tssop8 stm704s 2.925 so8 704s tssop8 stm704r 2.625 so8 704r tssop8 stm795t 3.075 so8 795t tssop8 stm795s 2.925 so8 795s tssop8 stm795r 2.625 so8 795r tssop8 stm802t 3.075 so8 802t tssop8 stm802s 2.925 so8 802s tssop8 stm802r 2.625 so8 802r tssop8 stm804t 3.075 so8 804t tssop8 stm804s 2.925 so8 804s tssop8 stm804r 2.625 so8 804r tssop8 stm805t 3.075 so8 805t tssop8 stm805s 2.925 so8 805s tssop8 stm805r 2.625 so8 805r tssop8 stm806t 3.075 so8 806t tssop8 stm806s 2.925 so8 806s tssop8 stm806r 2.625 so8 806r tssop8
31/32 stm690/704/ 795/802/804/805/806 revision history table 12. document revision history date version revision details october 31, 2003 1.0 first issue 22-dec-03 2.0 reformatted; update characteristics (figure 1 , 3 , 4 , 11 , 13 , 14 , 37 ; table 1 , 3 , 4 , 7 , 9 , 11 ) 16-jan-04 2.1 add typical operating characteristics (figure 17 , 18 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 29 , 30 , 31 , 32 , 33 , 34 ) 07-apr-04 2.2 update characteristics (figure 13 , 29 , 30 , table 1 , 3 , 7 ) 25-may-04 3.0 update characteristics (table 3 , 7 ) 02-jul-04 4.0 update package availability, pin description; promote document (figure 1 , 14 ; table 3 , 10 ) 29-sep-04 5.0 clarify root part numbers, pin descriptions, update characteristics (figure 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 13 , 14 , 35 ; table 1 , 3 , 6 , 7 , 10 ) 25-feb-05 6.0 update characteristics (figure 11 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 ; table 7 )
stm690/704/ 795/802/804/805/806 32/32 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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